On Wed, Mar 10, 2010 at 9:31 PM, Mark Brown broonie@opensource.wolfsonmicro.com wrote:
On Wed, Mar 10, 2010 at 04:48:52PM +0900, Jassi Brar wrote:
For some CPU-CODEC and source clock combination we might need to set BCLK to N*Sample_size*LRCLK, where N may be even 3 or 4, not just 2.
We can simply remove the dependency of BCLK on sample size as there is already a callback(S3C_I2SV2_DIV_BCLK) available to set required BCLK.
I've applied this but I'd rather see the code changed so that the BCLK is set automatically by default and the explict divider configuration disables that. This way we get the best of both worlds - most users won't need to worry about the BCLK configuration but those that need to configure it can do so. An awful lot of users don't really understand audio hardware and find having to learn about which clock rates they need and so on a bit of a learning curve.
I was thinking of calculating all register field values within the CPU driver and let MACHINE driver specify only general parameters of audio(as in many CODEC drivers). After this patch series, though.