21 May
2010
21 May
'10
11:49 a.m.
On Thu, 2010-05-20 at 17:53 -0500, Jorge Eduardo Candelaria wrote:
When using MCLK is configured for 19.2 Mhz, clock slicer should be enabled and HPPLL should be bypassed in clock path.
Signed-off-by: Jorge Eduardo Candelaria jorge.candelaria@ti.com Signed-off-by: Margarita Olaya Cabrera magi.olaya@ti.com
Applied.
Thanks
Liam
--
Freelance Developer, SlimLogic Ltd
ASoC and Voltage Regulator Maintainer.
http://www.slimlogic.co.uk