-----Original Message----- From: Takashi Iwai [mailto:tiwai@suse.de] Sent: Tuesday, August 02, 2011 7:09 PM To: Dong Aisheng-B29396 Cc: Mark Brown; alsa-devel@alsa-project.org; s.hauer@pengutronix.de; lrg@ti.com; linux-arm-kernel@lists.infradead.org; w.sang@pengutronix.de Subject: Re: [alsa-devel] [PATCH 1/1] ASoC: core: cache index fix
reg_cache_size is supposed to be the real size of the cache table. This isn't influenced by reg_cache_step value. So, the behavior in soc- io.c (and other ASoC core) is correct.
But the reg is related to step. So reg and reg_cache_size are un-match when step > 1, right?
I'm not sure what is referred here as reg, but the argument passed to snd_soc_{read|write}() is the raw register index. reg = 2 is 2 no matter whether reg_cache_step is 1 or 2. This is passed down to hw_read(), thus reg and reg_cache_size do match even when step > 1.
Yes, it is raw register index here. The case is that cache array is [reg0, reg1, reg2, reg3], So the size is 4. But when step is 2, reg0 is 0x0, reg1 is 0x2, reg3 is 0x6. So check if reg3 > reg_cache_size is not correct. I mean this mismatch. Am I correct?
Regards Dong Aisheng