From: Maruthi Srinivas Bayyavarapu Maruthi.Bayyavarapu@amd.com
Replaced usage of bitfield logic with alternative
Signed-off-by: Maruthi Bayyavarapu maruthi.bayyavarapu@amd.com Reviewed- by: Alex Deucher alexander.deucher@amd.com --- drivers/gpu/drm/amd/acp/acp_hw.c | 61 +++++++++++++++++----------------------- drivers/gpu/drm/amd/acp/acp_hw.h | 22 +-------------- 2 files changed, 27 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/amd/acp/acp_hw.c b/drivers/gpu/drm/amd/acp/acp_hw.c index 7ee2aa6..744d908 100644 --- a/drivers/gpu/drm/amd/acp/acp_hw.c +++ b/drivers/gpu/drm/amd/acp/acp_hw.c @@ -131,7 +131,7 @@ static void config_dma_descriptor_in_sram(struct amd_acp_device *acp_dev, cgs_write_register(acp_prv->cgs_device, mmACP_SRBM_Targ_Idx_Addr, (sram_offset + 8)); cgs_write_register(acp_prv->cgs_device, mmACP_SRBM_Targ_Idx_Data, - descr_info->size_xfer_dir.val); + descr_info->xfer_val); }
/* Initialize the DMA descriptor information for transfer between @@ -147,48 +147,44 @@ static void set_acp_sysmem_dma_descriptors(struct amd_acp_device *acp_dev,
num_descr = 2;
- dmadscr[0].size_xfer_dir.val = (u32) 0x0; + dmadscr[0].xfer_val = 0; if (direction == STREAM_PLAYBACK) { dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; dmadscr[0].dest = ACP_SHARED_RAM_BANK_1_ADDRESS + (size / 2); dmadscr[0].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + (pte_offset * PAGE_SIZE_4K); - dmadscr[0].size_xfer_dir.s.trans_direction = - ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM; - dmadscr[0].size_xfer_dir.s.size = (size / 2); - dmadscr[0].size_xfer_dir.s.ioc = (u32) 0x0; + dmadscr[0].xfer_val |= (DISABLE << 22) | + (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) | + (size / 2); } else { dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14; dmadscr[0].src = ACP_SHARED_RAM_BANK_5_ADDRESS; dmadscr[0].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + (pte_offset * PAGE_SIZE_4K); - dmadscr[0].size_xfer_dir.s.trans_direction = - ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION; - dmadscr[0].size_xfer_dir.s.size = size / 2; - dmadscr[0].size_xfer_dir.s.ioc = (u32) 0x1; + dmadscr[0].xfer_val |= + (ENABLE << 22) | + (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) | + (size / 2); }
config_dma_descriptor_in_sram(acp_dev, dma_dscr_idx, &dmadscr[0]);
- dmadscr[1].size_xfer_dir.val = (u32) 0x0; + dmadscr[1].xfer_val = 0; if (direction == STREAM_PLAYBACK) { dma_dscr_idx = PLAYBACK_END_DMA_DESCR_CH12; dmadscr[1].dest = ACP_SHARED_RAM_BANK_1_ADDRESS; dmadscr[1].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + (pte_offset * PAGE_SIZE_4K) + (size / 2); - dmadscr[1].size_xfer_dir.s.trans_direction = - ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM; - dmadscr[1].size_xfer_dir.s.size = (size / 2); - dmadscr[1].size_xfer_dir.s.ioc = (u32) 0x0; + dmadscr[1].xfer_val |= (DISABLE << 22) | + (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) | + (size / 2); } else { dma_dscr_idx = CAPTURE_END_DMA_DESCR_CH14; - dmadscr[1].size_xfer_dir.s.trans_direction = - ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION; - dmadscr[1].size_xfer_dir.val = (u32) 0x0; dmadscr[1].dest = dmadscr[0].dest + (size / 2); dmadscr[1].src = dmadscr[0].src + (size / 2); - dmadscr[1].size_xfer_dir.s.size = (size / 2); - dmadscr[1].size_xfer_dir.s.ioc = (u32) 0x1; + dmadscr[1].xfer_val |= (ENABLE << 22) | + (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) | + (size / 2); }
config_dma_descriptor_in_sram(acp_dev, dma_dscr_idx, &dmadscr[1]); @@ -221,37 +217,32 @@ static void set_acp_to_i2s_dma_descriptors(struct amd_acp_device *acp_dev,
num_descr = 2;
- dmadscr[0].size_xfer_dir.val = (u32) 0x0; + dmadscr[0].xfer_val = 0; if (direction == STREAM_PLAYBACK) { dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; dmadscr[0].src = ACP_SHARED_RAM_BANK_1_ADDRESS; - dmadscr[0].size_xfer_dir.s.trans_direction = TO_ACP_I2S_1; - dmadscr[0].size_xfer_dir.s.size = (size / 2); - dmadscr[0].size_xfer_dir.s.ioc = (u32) 0x1; + dmadscr[0].xfer_val |= (ENABLE << 22) | (TO_ACP_I2S_1 << 16) | + (size / 2); } else { dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15; dmadscr[0].dest = ACP_SHARED_RAM_BANK_5_ADDRESS; - dmadscr[0].size_xfer_dir.s.trans_direction = FROM_ACP_I2S_1; - dmadscr[0].size_xfer_dir.s.size = (size / 2); - dmadscr[0].size_xfer_dir.s.ioc = (u32) 0x1; + dmadscr[0].xfer_val |= (ENABLE << 22) | + (FROM_ACP_I2S_1 << 16) | (size / 2); }
config_dma_descriptor_in_sram(acp_dev, dma_dscr_idx, &dmadscr[0]);
- dmadscr[1].size_xfer_dir.val = (u32) 0x0; + dmadscr[1].xfer_val = 0; if (direction == STREAM_PLAYBACK) { dma_dscr_idx = PLAYBACK_END_DMA_DESCR_CH13; dmadscr[1].src = dmadscr[0].src + (size / 2); - dmadscr[1].size_xfer_dir.s.trans_direction = TO_ACP_I2S_1; - dmadscr[1].size_xfer_dir.s.size = (size / 2); - dmadscr[1].size_xfer_dir.s.ioc = (u32) 0x1; - + dmadscr[1].xfer_val |= (ENABLE << 22) | (TO_ACP_I2S_1 << 16) | + (size / 2); } else { dma_dscr_idx = CAPTURE_END_DMA_DESCR_CH15; dmadscr[1].dest = dmadscr[0].dest + (size / 2); - dmadscr[1].size_xfer_dir.s.trans_direction = FROM_ACP_I2S_1; - dmadscr[1].size_xfer_dir.s.size = (size / 2); - dmadscr[1].size_xfer_dir.s.ioc = (u32) 0x1; + dmadscr[1].xfer_val |= (ENABLE << 22) | + (FROM_ACP_I2S_1 << 16) | (size / 2); }
config_dma_descriptor_in_sram(acp_dev, dma_dscr_idx, &dmadscr[1]); diff --git a/drivers/gpu/drm/amd/acp/acp_hw.h b/drivers/gpu/drm/amd/acp/acp_hw.h index b58349c..e3a102c 100644 --- a/drivers/gpu/drm/amd/acp/acp_hw.h +++ b/drivers/gpu/drm/amd/acp/acp_hw.h @@ -73,26 +73,6 @@ enum { ACP_DMA_ATTRIBUTES_FORCE_SIZE = 0xF };
-typedef struct acp_dma_dscr_size_transfer_direction { - /* Specifies the number of bytes need to be transferred - * from source to destination memory. */ - u32 size:16; - /* Specifies transfer direction. */ - u32 trans_direction:4; - /* reserved. */ - u32 reserved1:2; - /* Specifies the IOC enable or not for descriptor. */ - /* Defaultly this will be 0, for the last descriptor, make it Enable */ - u32 ioc:1; - /* reserved. */ - u32 reserved2:9; -} acp_dma_dscr_size_transfer_direction_t; - -typedef union { - u32 val:32; - acp_dma_dscr_size_transfer_direction_t s; -} acp_dma_dscr_size_transfer_direction_u; - typedef struct acp_dma_dscr_transfer { /* Specifies the source memory location for the DMA data transfer. */ u32 src; @@ -103,7 +83,7 @@ typedef struct acp_dma_dscr_transfer { /* Specifies the number of bytes need to be transferred * from source to destination memory.Transfer direction & IOC enable */ - acp_dma_dscr_size_transfer_direction_u size_xfer_dir; + u32 xfer_val; /** Reserved for future use */ u32 reserved; } acp_dma_dscr_transfer_t;