30 Jan
2015
30 Jan
'15
10:50 p.m.
Hi Eric,
On 01/30/2015 11:31 PM, Fabio Estevam wrote:
Hi Eric,
On Fri, Jan 30, 2015 at 7:07 PM, Eric Nelson eric.nelson@boundarydevices.com wrote:
To quote from section 1.3.1 of the data sheet: The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLK cycles after all power rails have been brought up. After this time, communication can start
... 1.0uS represents 8 SYS_MCLK cycles at the minimum 8.0 MHz SYS_MCLK.Small detail: Should be us instead of uS.
FYI - If you're observing issues with communicating with SGTL5000 I2C, please make sure also that the chip has a valid clock signal on SYS_MCLK, otherwise it won't respond on I2C transactions (I2C will work with any SYS_MCLK in the range 8-27MHz).
Kind regards, Nikolay