Hi Phillip,
glad to see someone is wasting time with that issue, too :)
On Tue, Mar 03, 2009 at 04:10:51PM +0100, Philipp Zabel wrote:
For consistency with 24-bit and 32-bit modes, don't send 16-bit stereo in one 32-bit transfer. Use 2 slots instead on Zylonite. It should result in exactly the same behaviour. Now it is possible to use 16-bit single slot transfers in pxa-ssp, which are needed for Magician to get two frame clock pulses per sample (one for each channel).
We've been fiddling around with these modes and registers for another two days in a row now and figured out that literally all the documentation about these registers is entirly bogus. In particular, the network mode with the associated timeslots simply does not work at all, according to our measurements.
Hence the question: how does your I2S signal look like at the moment? How many clocks do you measure in one frame cylce, how many of them are actually filled with data? And which format does the userspace use to send samples in?
We finally got a mode now that outputs 2x16 bit on a 2x32 bits I2S frame, padded with zeros. But that is in non-network modes, more about that tomorrow ...
Thanks, Daniel