8 Aug
2016
8 Aug
'16
12:32 p.m.
On 08 August 2016 08:43, Peter Meerwald-Stadler wrote:
Currently the handling of the PLL in the driver is a little clunky, and not ideal for all modes. This patch updates the code to make it cleaner and more sensible for the various PLL states.
Key items of note are:
- MCLK squaring is now handled directly as part of the sysclk() function, removing the need for a private flag to set this feature.
- All PLL modes are defined as an enum, and are handled as a case statement in pll() function to clean up configuration. This also removes any need for a private flag for SRM.
- For 32KHz mode, checks are made on codec master mode and correct MCLK rates, to avoid incorrect usage of PLL for this operation.
- For 32KHz mode, SRM flag now correctly enabled and fout set to sensible value to achieve appropriate PLL dividers.
thanks, looks good Tested-by: Peter Meerwald-Stadler pmeerw@pmeerw.net
nitpick: add extra newline at the end of if (da7213->mclk_rate == 32768) block
Thanks. Glad the patch set has resolved issues you were seeing. Patches have been pulled by Mark.