2014-10-09 17:19 GMT+02:00 Fabio Estevam festevam@gmail.com:
On Thu, Oct 9, 2014 at 12:14 PM, Jean-Michel Hautbois jean-michel.hautbois@vodalys.com wrote:
Ouch, nice catch :).
Here is what I understand, in my cas, sgtl5000 has its clock routed through a FPGA. If the FPGA has not yet be probed, then, the module fails in loading : [ 4.985762] sgtl5000: probe of 1-000a failed with error -5
This is why after removing it and probing it again manually, it works.
This module should be able to defer probing too, is it going to be done by someone or do I try to send some patch for this ?
We do defer probing already:
sgtl5000->mclk = devm_clk_get(&client->dev, NULL); if (IS_ERR(sgtl5000->mclk)) { ret = PTR_ERR(sgtl5000->mclk); dev_err(&client->dev, "Failed to get mclock: %d\n", ret); /* Defer the probe to see if the clk will be provided later */ if (ret == -ENOENT) return -EPROBE_DEFER; return ret; }
Yes, sorry about that, missed it.
BTW, I don't have sound on the microphone input, and I think there is no way to select micbias voltage level neither from the source code nor the DT ? It could be interetsing to have something like sgtl5000-micbias-vg which would give control on the voltage bias parameter ? And maybe also something for bias resistor too ?
I can try to patch something.
That would be great, thanks.
Do I need to keep actual defaults if the resistor or voltage are not specified in DT ? Or should I set it to off (which is probably more logical) ? And one or two patches (one resistor and one voltage patch, or both in the same) ?
JM