On Mon, Nov 07, 2011 at 09:19:07PM +0100, Clemens Ladisch wrote:
Daniel Mack wrote:
I guess this is some sort of a race condition in the stream startup, and suspected sound/soc/pxa/pxa-ssp.c to lack some locking, so I added a spinlock around all register read-modify-write cycles. But that doesn't seem to be the reason.
I'd guess this is a race in the programming of the L/R clock signals; try putting a lock/mutex about all the stream initialization code, and maybe adding some delay.
That's very unlikely to help, these issues are generally issues with the controller not being able to figure out which clock edge to start on properly and if there are problems here locking is unlikely to help - the issue is the two hardware blocks synchronizing with each other, usually with the clocks driven from an asynchronous domain.