On Mon, Dec 03, 2018 at 12:23:11AM +0300, Mesih Kilinc wrote:
DMA of Allwinner suniv F1C100s is similar to sun4i. It has 4 NDMA, 4 DDMA channels and endpoints are different. Also F1C100s has reset bit for DMA in CCU. Add support for it.
Signed-off-by: Mesih Kilinc mesihkilinc@gmail.com
drivers/dma/Kconfig | 4 ++-- drivers/dma/sun4i-dma.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index de511db..f8a65d2 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -163,8 +163,8 @@ config DMA_SA11X0
config DMA_SUN4I tristate "Allwinner A10 DMA SoCs support"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
- default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV
- default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV) select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help
diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index d267ff9..c0452c9 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -36,7 +36,11 @@ #define SUN4I_DMA_CFG_SRC_ADDR_MODE(mode) ((mode) << 5) #define SUN4I_DMA_CFG_SRC_DRQ_TYPE(type) (type)
+#define SUNIV_DMA_CFG_DST_DATA_WIDTH(width) ((width) << 24) +#define SUNIV_DMA_CFG_SRC_DATA_WIDTH(width) ((width) << 8)
#define SUN4I_MAX_BURST 8 +#define SUNIV_MAX_BURST 4
/** Normal DMA register values **/
@@ -44,6 +48,9 @@ #define SUN4I_NDMA_DRQ_TYPE_SDRAM 0x16 #define SUN4I_NDMA_DRQ_TYPE_LIMIT (0x1F + 1)
+#define SUNIV_NDMA_DRQ_TYPE_SDRAM 0x11 +#define SUNIV_NDMA_DRQ_TYPE_LIMIT (0x17 + 1)
/** Normal DMA register layout **/
/* Dedicated DMA source/destination address mode values */ @@ -57,6 +64,9 @@ #define SUN4I_NDMA_CFG_BYTE_COUNT_MODE_REMAIN BIT(15) #define SUN4I_NDMA_CFG_SRC_NON_SECURE BIT(6)
+#define SUNIV_NDMA_CFG_CONT_MODE BIT(29) +#define SUNIV_NDMA_CFG_WAIT_STATE(n) ((n) << 26)
/** Dedicated DMA register values **/
/* Dedicated DMA source/destination address mode values */ @@ -69,6 +79,9 @@ #define SUN4I_DDMA_DRQ_TYPE_SDRAM 0x1 #define SUN4I_DDMA_DRQ_TYPE_LIMIT (0x1F + 1)
+#define SUNIV_DDMA_DRQ_TYPE_SDRAM 0x1 +#define SUNIV_DDMA_DRQ_TYPE_LIMIT (0x9 + 1)
/** Dedicated DMA register layout **/
/* Dedicated DMA configuration register layout */ @@ -122,6 +135,11 @@ #define SUN4I_DMA_NR_MAX_VCHANS \ (SUN4I_NDMA_NR_MAX_VCHANS + SUN4I_DDMA_NR_MAX_VCHANS)
+#define SUNIV_NDMA_NR_MAX_CHANNELS 4 +#define SUNIV_DDMA_NR_MAX_CHANNELS 4 +#define SUNIV_NDMA_NR_MAX_VCHANS (24 * 2 - 1) +#define SUNIV_DDMA_NR_MAX_VCHANS 10
/* This set of SUN4I_DDMA timing parameters were found experimentally while
- working with the SPI driver and seem to make it behave correctly */
#define SUN4I_DDMA_MAGIC_SPI_PARAMETERS \ @@ -236,6 +254,16 @@ static void set_src_data_width_a10(u32 *p_cfg, s8 data_width) *p_cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(data_width); }
+static void set_dst_data_width_f1c100s(u32 *p_cfg, s8 data_width) +{
- *p_cfg |= SUNIV_DMA_CFG_DST_DATA_WIDTH(data_width);
+}
+static void set_src_data_width_f1c100s(u32 *p_cfg, s8 data_width) +{
- *p_cfg |= SUNIV_DMA_CFG_SRC_DATA_WIDTH(data_width);
+}
static int convert_burst_a10(u32 maxburst) { if (maxburst > 8) @@ -245,6 +273,15 @@ static int convert_burst_a10(u32 maxburst) return (maxburst >> 2); }
+static int convert_burst_f1c100s(u32 maxburst) +{
- if (maxburst > 4)
return -EINVAL;- /* 1 -> 0, 4 -> 1 */
- return (maxburst >> 2);
+}
This is essentially the same function than for the A10, with a different limit. Like a was saying, use a bitmask for the supported bursts length, and test whether the burst is supported against that mask. You won't have to duplicate those functions anymore.