4 Feb
2016
4 Feb
'16
6:24 p.m.
On 02/04/2016 06:22 PM, Lars-Peter Clausen wrote: [...]
- /* Enable cache only mode as we could miss writes before bias level
* reaches standby and the core clock is enabled */- regcache_cache_only(regmap, true);
There are a few register writes before this where the hardware configuration is setup. When I look at my test setup those writes seem to go through, even though they shouldn't according to what you say (and to what is written in the datasheet).
On the other hand I've never seen the issue you are having either and I've tested both master and slave configuration of the device. Maybe something changed in the silicon in newer revisions of the device. Can you take a look whether the hardware configuration is correctly applied for you?
Ah, no, ignore that. Those writes happen later on.