On Tue, Feb 03, 2009 at 01:46:32AM +0200, Vasily Khoruzhick wrote:
and later aplay). It's bug in uda1380 driver (probably, just a typo), driver switches to WSPLL in uda1380_pcm_prepare even if SYSCLK was chosen (uda1380_pcm_prepare modifies UDA1380_CLK register before flushing reg cache, but doesn't restore its value later)
Your explanation here makes sense but...
One more question: it seems that my rx1950 clocked in a way that I can't get precise divisor for 44100 and 22050 rates, but uda1380 driver propose them (look UDA1380_RATES define and struct snd_soc_dai uda1380_dai[]. How to exclude all rates except 16000 and 48000? Should I declare my own snd_soc_dai and copy necessary members from uda1380's one?
Set up additional constraints in your machine driver - see how drivers like wm8903 enforce symmetric configurations for playback and record for an example.
/* FIXME enable DAC_CLK */
- uda1380_write(codec, UDA1380_CLK, clk | R00_DAC_CLK);
- uda1380_write(codec, UDA1380_CLK, clk);
..are you sure this fix won't break existing users? Based on your explanation above (which should *really* go into the commit) I'd expect this to be conditional on something. It looks like what you really want to do here is clean up the FIXMEs :)