24 Apr
2017
24 Apr
'17
2:12 p.m.
On 04/22/2017 04:51 AM, Stephen Boyd wrote:
+static int samsung_pll3xxx_enable(struct clk_hw *hw) +{
- struct samsung_clk_pll *pll = to_clk_pll(hw);
- u32 tmp;
- tmp = readl_relaxed(pll->con_reg);
- tmp |= BIT(pll->enable_offs);
- writel_relaxed(tmp, pll->con_reg);
- /* wait lock time */
- do {
cpu_relax();tmp = readl_relaxed(pll->con_reg);- } while (!(tmp & BIT(pll->lock_offs)));
Not a problem with this patch because we're moving code around, but this is a potential infinite loop that should have some sort of timeout so we don't sit here forever trying to see a bit toggle.
Yes, I will add some protection in new patch, like it is done for newer PLLs. Thanks for you review.
--
Regards,
Sylwester