When ACP enters D0 state, after executing acp soft reset sequence, all acp registers will be set to default values. To handle ACP D0 & SoundWire D3 scenario wake events, Soundwire host wake interrupt mask should be reprogrammed.
Enable SoundWire host wake irq mask during acp init sequence.
Signed-off-by: Vijendar Mukunda Vijendar.Mukunda@amd.com --- sound/soc/amd/acp70/acp70.h | 1 + sound/soc/amd/acp70/pci-acp70.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+)
diff --git a/sound/soc/amd/acp70/acp70.h b/sound/soc/amd/acp70/acp70.h index ab4d6a5c1cd2..232210df6f10 100644 --- a/sound/soc/amd/acp70/acp70.h +++ b/sound/soc/amd/acp70/acp70.h @@ -139,6 +139,7 @@
/* time in ms for runtime suspend delay */ #define ACP_SUSPEND_DELAY_MS 2000 +#define ACP_SDW_HOST_WAKE_MASK 0x0C00000
enum acp_config { ACP_CONFIG_0 = 0, diff --git a/sound/soc/amd/acp70/pci-acp70.c b/sound/soc/amd/acp70/pci-acp70.c index ff03fd493e98..79b0ab96217b 100644 --- a/sound/soc/amd/acp70/pci-acp70.c +++ b/sound/soc/amd/acp70/pci-acp70.c @@ -52,10 +52,25 @@ static int acp70_reset(void __iomem *acp_base) return readl_poll_timeout(acp_base + ACP_SOFT_RESET, val, !val, DELAY_US, ACP_TIMEOUT); }
+static void acp70_enable_sdw_host_wake_interrupts(void __iomem *acp_base) +{ + u32 ext_intr_cntl1; + + ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1); + ext_intr_cntl1 |= ACP_SDW_HOST_WAKE_MASK; + writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1); +} + static void acp70_enable_interrupts(void __iomem *acp_base) { + u32 sdw0_wake_en, sdw1_wake_en; + writel(1, acp_base + ACP_EXTERNAL_INTR_ENB); writel(ACP_ERROR_IRQ, acp_base + ACP_EXTERNAL_INTR_CNTL); + sdw0_wake_en = readl(acp_base + ACP_SW0_WAKE_EN); + sdw1_wake_en = readl(acp_base + ACP_SW1_WAKE_EN); + if (sdw0_wake_en || sdw1_wake_en) + acp70_enable_sdw_host_wake_interrupts(acp_base); }
static void acp70_disable_interrupts(void __iomem *acp_base)