On Thu, 10 Nov 2022 at 12:39, Linus Walleij linus.walleij@linaro.org wrote:
On Thu, Nov 10, 2022 at 12:29 PM Ulf Hansson ulf.hansson@linaro.org wrote:
On Fri, 4 Nov 2022 at 14:32, Maxime Ripard maxime@cerno.tech wrote:
The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent hook, but doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate.
The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock.
If I recall correctly, that is the use case we did target for these types of clocks. See sound/soc/ux500/ux500_ab85xx.c, for example.
Hm I am trying to get that driver to work ... from time to time. It's just that ALSA SoC DT has changed to much that it turns out into a complete rewrite :/
So in sound/soc/ux500/mop500_ab8500.c I see this:
status = clk_set_parent(drvdata->clk_ptr_intclk, clk_ptr); if (status)(...)
and there is elaborate code to switch between "SYSCLK" and "ULPCLK" (ulta-low power clock). Just like you say... however a clock named SYSCLK or ULPCLK does not appear in the code in drivers/clk/ux500 or any DT bindings so... it seems to be non-working for the time being.
It's definitely not working, but the corresponding clocks ("ulpclk", "intclk", "audioclk", etc) are being registered in ab8500_reg_clks().
What seems to be missing is a DT conversion for these clocks, so they can be consumed properly. Right?
Kind regards Uffe