According to the datasheet:
MIC Power Control & Speed Control (Address 03h) BIT[7] : Auto-Detect Speed Mode (AUTO) Default: 1 0 - Disable 1 - Enable
Function: Enables the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a slave. When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 39. The SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
SPEED[1:0] bits are ignored when this bit is enabled. Thus we need to clear this bit for MODE_SLAVE and MODE_MASTER because the default of this bit is 1 (Enable).
Signed-off-by: Axel Lin axel.lin@gmail.com --- sound/soc/codecs/cs42l51.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c index 00718b5..35c5ac3 100644 --- a/sound/soc/codecs/cs42l51.c +++ b/sound/soc/codecs/cs42l51.c @@ -400,7 +400,8 @@ static int cs42l51_hw_params(struct snd_pcm_substream *substream,
intf_ctl &= ~(CS42L51_INTF_CTL_MASTER | CS42L51_INTF_CTL_ADC_I2S | CS42L51_INTF_CTL_DAC_FORMAT(7)); - power_ctl &= ~(CS42L51_MIC_POWER_CTL_SPEED(3) + power_ctl &= ~(CS42L51_MIC_POWER_CTL_AUTO + | CS42L51_MIC_POWER_CTL_SPEED(3) | CS42L51_MIC_POWER_CTL_MCLK_DIV2);
switch (cs42l51->func) {