Am Freitag, den 16.01.2015, 11:15 +0200 schrieb Peter Ujfalusi:
On 01/16/2015 12:28 AM, Thomas Niederprüm wrote:
This patch fixes faulty behaviour in a setup where the input clock for the SRG is fed through the CLKR pin but the McBSP is configured to be master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR must not be configured as output pin. Otherwise the input clock is messed up horribly. The same reasoning applies if CLKX is configured as input for the SRG.
If CLKX/CLKR is used as input clock for McBSP then the CBS_CFS is not valid. In this case you need to use CBM_CFS.
The setup I am using is the following: McBSP is driving an external i2s DAC as master by supplying CLKX and FSX and DX. The DAC only supports i2s slave mode. For synchronization the DAC and the McBSP should share the same master/reference clock (CLKM). Since I don't need the receive path of the McBSP anyway for the DAC I can use the CLKR pin to insert the CLKM as input to the SRG. I think in this scenario CBS_CFS is valid since the McBSP acts as master (for the transmit path)
It might be more common to use the CKLS pin to inject the reference clock, but the beagleboard-xm I am using already hard wired this to the built-in twl4030 codec which makes it unusable.
Signed-off-by: Thomas Niederprüm niederp@physik.uni-kl.de
sound/soc/omap/omap-mcbsp.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index bd3ef2a..c89f562 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -530,8 +530,12 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
case OMAP_MCBSP_SYSCLK_CLKX_EXT: regs->srgr2 |= CLKSM;
regs->pcr0 |= SCLKME;regs->pcr0 &= ~CLKXM;break;regs->pcr0 &= ~CLKRM;