On 6/2/22 18:33, Mark Brown wrote:
On Thu, Jun 02, 2022 at 05:57:43PM +0800, Hui Wang wrote:
On 2022/5/30 下午 12:01, Hui Wang wrote: So when the playback/recording starts, the PLL parameters from Reg 0x25~0x27 will be always set before Reg 0x1[5] power enable bit(PLLEN). When the playback/recording stops, the PLLEN will be disabled. Thanks for your comment. But it is weird, it doesn't work like you said,
On 6/2/22 17:24, David Lin wrote: probably need specific route setting in the machine driver level? Is this triggering due to reprogramming the PLL for one direction while the other is already active (eg, starting a capture during a playba
Yes, it is. With the current machine driver of fsl-asoc-card.c, if starting a capture during a playback or starting a playback during a capture, the codec driver will reprogram PLL parameters while PLL is on. And in another case, if the snd_soc_dai_set_pll() is called in the card->set_bias_level() instead of card_hw_params(), the PLL will keep being off since check_mclk_select_pll() always returns false. Thanks.