Setting the DATALEN bit field requires shifting our value by 4. Setting the OSR value of the PLL divider also requires a shift by 4. Currently the code abuses this fact and uses the shift for the divider register to set the data-length register. Fix this here by using the definition meant for this register.
Signed-off-by: Andrew F. Davis afd@ti.com --- sound/soc/codecs/tlv320aic32x4.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 01e65d768cab..b3b1ca96bb69 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -722,15 +722,20 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream, data = data & ~(3 << 4); switch (params_width(params)) { case 16: + data |= (AIC32X4_WORD_LEN_16BITS << + AIC32X4_IFACE1_DATALEN_SHIFT); break; case 20: - data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT); + data |= (AIC32X4_WORD_LEN_20BITS << + AIC32X4_IFACE1_DATALEN_SHIFT); break; case 24: - data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT); + data |= (AIC32X4_WORD_LEN_24BITS << + AIC32X4_IFACE1_DATALEN_SHIFT); break; case 32: - data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT); + data |= (AIC32X4_WORD_LEN_32BITS << + AIC32X4_IFACE1_DATALEN_SHIFT); break; } snd_soc_write(codec, AIC32X4_IFACE1, data);