Couch, Kelly J wrote:
I'm designing software for a specific test application that will utilize an Intel HD audio controller. I must verify the functionality of several sets of TDM audio signals (CK, FS, TXD, RXD) from the Intel HD Audio controller. In this scenario, the Intel HD Audio controller is NOT connected directly to a CODEC, but to a header. My proposal is to connect these signals directly to an FPGA, using it to loopback the data (in various permutations of loopback to channels) to verify each of the signals.
Let's see what the spec says: | SDO – Serial Data Out: [...] Data is double pumped – i.e., the | controller drives data onto SDO, and codecs sample data present on | SDO with respect to every edge of BCLK. [...] | SDI – Serial Data In: [...] Data is single pumped; codecs drive SDI | and the controller samples SDI with respect to the rising edge of | BCLK.
Oh, and outbound and inbound frames use a different format.
I guess this why you're using an FPGA instead of a wire? :)
Because the FPGA will be in place of a real CODEC device, I'm concerned with how the software side of this approach will work?
The ALSA driver tries to detect the capabilities of the codec(s). You would have to replace all codec read accesses with hardcoded values that describe a virtual codec with a suitable widget topology.
Regards, Clemens