Hi,
On Tue, Oct 15, 2024, Wesley Cheng wrote:
From: Mathias Nyman mathias.nyman@linux.intel.com
Introduce XHCI sideband, which manages the USB endpoints being requested by a client driver. This is used for when client drivers are attempting to offload USB endpoints to another entity for handling USB transfers. XHCI sideband will allow for drivers to fetch the required information about the transfer ring, so the user can submit transfers independently. Expose the required APIs for drivers to register and request for a USB endpoint and to manage XHCI secondary interrupters.
Multiple ring segment page linking, proper endpoint clean up, and allowing module compilation added by Wesley Cheng to complete original concept code by Mathias Nyman.
Signed-off-by: Mathias Nyman mathias.nyman@linux.intel.com Co-developed-by: Wesley Cheng quic_wcheng@quicinc.com Signed-off-by: Wesley Cheng quic_wcheng@quicinc.com
drivers/usb/host/Kconfig | 9 + drivers/usb/host/Makefile | 2 + drivers/usb/host/xhci-sideband.c | 424 ++++++++++++++++++++++++++++++ drivers/usb/host/xhci.h | 4 + include/linux/usb/xhci-sideband.h | 70 +++++ 5 files changed, 509 insertions(+) create mode 100644 drivers/usb/host/xhci-sideband.c create mode 100644 include/linux/usb/xhci-sideband.h
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 4448d0ab06f0..96659efa4be5 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -104,6 +104,15 @@ config USB_XHCI_RZV2M Say 'Y' to enable the support for the xHCI host controller found in Renesas RZ/V2M SoC.
+config USB_XHCI_SIDEBAND
- tristate "xHCI support for sideband"
- help
Say 'Y' to enable the support for the xHCI sideband capability.Provide a mechanism for a sideband datapath for payload associated
Please correct me if I'm wrong, but this doesn't look like the actual xHCI Audio Sideband capability described in the xHCI spec section 7.9 but rather a specific implementation for Qcom right? For the xHCI Audio Sideband xHCI capability, the driver should detect this capability through the xHCI get extended capability. If this is not xHCI Audio Sideband capability, we should properly clarify this in the documentation and the naming of things to avoid any confusion.
I believe your implementation still needs to provide the data to the host controller through the system memory right? The xHCI Audio Sideband capability may pass the data to the xHC other than the main memory.
BR, Thinh
with audio class endpoints. This allows for an audio DSP to usexHCI USB endpoints directly, allowing CPU to sleep while playingaudio.config USB_XHCI_TEGRA tristate "xHCI support for NVIDIA Tegra SoCs" depends on PHY_TEGRA_XUSB