The Rockchip timer linux driver can handle a maximum of 2 timers and will get confused if more of them exist. RK3128 only needs timer0, timer1 and timer5. The latter is the source for the arm-timer and its clock is prevented from being disabled in the clock driver so it can get disabled in the device tree, too.
Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi") Signed-off-by: Alex Bee knaerzche@gmail.com --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 88a4b0d6d928..f3f0788195d2 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -252,6 +252,7 @@ timer2: timer@20044040 { interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>; clock-names = "pclk", "timer"; + status = "disabled"; };
timer3: timer@20044060 { @@ -260,6 +261,7 @@ timer3: timer@20044060 { interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>; clock-names = "pclk", "timer"; + status = "disabled"; };
timer4: timer@20044080 { @@ -268,6 +270,7 @@ timer4: timer@20044080 { interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>; clock-names = "pclk", "timer"; + status = "disabled"; };
timer5: timer@200440a0 { @@ -276,6 +279,7 @@ timer5: timer@200440a0 { interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>; clock-names = "pclk", "timer"; + status = "disabled"; };
watchdog: watchdog@2004c000 {