22 Feb
2024
22 Feb
'24
8:49 p.m.
On Mon, Jan 29, 2024 at 03:35:34PM +0100, Krzysztof Kozlowski wrote:
Starting with Qualcomm SM8350 SoC, so Low Power Audio SubSystem (LPASS) block version v9.2, the register responsible for TX SMIC MUXn muxes is different. In earlier LPASS versions this mux had bit fields for analogue (ADCn) and digital (SWR_DMICn) MICs. Choice of ADCn was selecting the analogue path in CDC_TX_TOP_CSR_SWR_DMICn_CTL register.
This doesn't apply against current code, please check and resend.