On 19/12/2019 17:14, Srinivas Kandagatla wrote:
+ if (sts & SWRM_INTERRUPT_STATUS_CMD_ERROR) { + ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value); + dev_err_ratelimited(ctrl->dev, + "CMD error, fifo status 0x%x\n", + value); + ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); + }
+ if ((sts & SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED) || + sts & SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS) + schedule_work(&ctrl->slave_work);
+ ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);
is it intentional to clear the interrupts first, before doing additional checks?
No, I can move it to right to the end!
Reason why I did this was that if we run complete() before irq is cleared complete might trigger another read/write which can raise an interrupt. And with interrupt status not cleared we might miss it. This is very much timing dependent specially with the threaded irq.
So code needs no change atm!
Or could it be done immediately after reading the status. It's not clear to me if the position of this clear matters, and if yes you should probably add a comment?
Am not 100% if it matters, but Ideally I would like clear the interrupt source before clearing the interrupt.
+ if (sts & SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED) { + spin_lock_irqsave(&ctrl->comp_lock, flags); + if (ctrl->comp) + complete(ctrl->comp); + spin_unlock_irqrestore(&ctrl->comp_lock, flags); + }
+ return IRQ_HANDLED;
The rest looks fine. nice work.
Thanks, srini