Hi Sylwester,
thank you for the explanation. I can follow the clock description in the DT and it looks like a reasonable approach. However neither the codec or I2S seem to implement any clock provider. How is the implementation side done? I mean someone needs to set the PLLs, etc.
Thanks Petr
On 10.12.2015 18:13, Sylwester Nawrocki wrote:
On 10/12/15 17:31, Petr Kulhavy wrote:
Hi,
I'm developing a DT-based driver for an ARM SoC device with the following special clock routing:
- WM8758 codec attached to the CPU DAI via I2S
- the codec is I2S clock master
- the CPU feeds the codec with 12MHz clock (outside of the I2S)
- the codec converts the 12MHz internally to 48kHz*256 or 44.1kHz *256
clock and provides it to I2S as MCLK
So the special set-up needed here is that the codec needs to be configured to: a) generate the proper MCLK b) enable the respective GPIO pin as clock output
What is the best way of representing this set-up using device tree? I'm wondering if this can be done by adding a specific option in the codec DT binding for enabling the clock output and then use the simple audio card. Or do I need to write a specific soundcard driver that sets up the codec registers? I would like to avoid that if possible and use existing code...
What would you recommend?
I assume when the clock enable/disable code is not there it could be added to the codec driver, e.g. like in case of max98090. The clock source just needs to be exposed as a common clock object.
As an example of similar setup you could take a look at arch/arm/boot/dts/exynos4412-odroid-common.dts. The difference was that in case of Odroid the clock was generated by a PLL inside a SoC, then it was routed to I2S which fed the clock to the codec through the SoC's io pin. The codec was I2S master and the I2S IP block was actually a source of its main ("mclk") clock. I hope this helps.