On Fri, Dec 19, 2014 at 10:13:32AM +0000, Aurelien Bouin wrote:
I have a bit doubt whether your problem is the underrun or not. Because I remember the work around submitter did test with underrun issue. The reset function would be trigger by the ESAI internal ISR but be called through the ISR from dma callback.
There's a fsl_esai_check_xrun() inside the ESAI. You can try to see if it's really underrun happened.
I also add a dump function that show the register at fsl_esai_hw_params : ESAI_TCR 0x00728100 I also add debug in the function fsl_esai_check_xrun that show the saisr register When underrun occured (when I see that with an oscilloscope)
There is no interrupt generated ...
So I suppose your 'no interrupt generated' also means that the underrun flag has never been set: even if you added check debug code into the fsl_esai_check_xrun(), it hasn't given you any feedback.
In that case, I think the channel swap was not resulted from ESAI hardware FIFO underrun.
I tried to change the transmit fifo watermak(These bits configure the threshold at which the Transmit FIFO Empty flag will set) to set it to a value of 2 Before I was using 64, since I use 64 channels in this case I get a lot of underrun interrupt ... and of course it is not working correctly .. Because the dma know to late that there is not enough data in the ESAI transmit FIFO...
Since you got the underrun error flag after you changed watermark, that also proves your previous channel swap issue was not trigger by the underrun issue.
And besides, which pins from IOMUX are you using for ESAI?
I am using TX0, TX1 and RX0, RX1
No, I'm asking the full pin name of IOMUX. Where's the TX0, TX1 come from the IOMUX. You can check you schematics or the pinctrl configuration in your dts/dtsi to see the name.
Another suggestion is for your mail client setting...please try to set your mail client to text/plain or auto-wrapping mode. We basically write code or mail no more than 80 characters per line.
--Nicolin