On Fri, Aug 14, 2015 at 02:22:53AM -0700, Nicolin Chen wrote:
I have to add Shawn for help :)
On Fri, Aug 14, 2015 at 03:38:16PM +0800, Zidan Wang wrote:
ccm ----->1------------------>2<------------>3 | | | | 4 SAIx MCLK1 5 SAIx MCLK2
If this bit is set, the clock route is ccm->1->2->3, 2 to 5 is disconnect. If this bit is clear, the clock route is 3->2->5, 1 to 2 is disconnect.
@Shawn
Suppose 1 and 2 are clock MUXs that we can't specifically touch via registers. And 3 is an IO PAD that can either output a clock from CCM or input a clock from an external source outside SoC. Both 4 and 5 are two clock sources for one single SAI, SAI2 for example.
There is a bit in the GPR register to control above routes. And my question is where should be the best place to put this bit.
If this route selection is a decision of board design, it should fit device tree quite well. As the platform maintainer, I surely hope we can handle this in audio driver. But if there is really no place better than platform code to handle it, I can accept it.
Shawn
Apparently it's outside the CCM and SAI, not to mention it is hard to relate this bit to this ASoC dai-link driver which's supposed to solve problems between the SAI and CODECs.
Thanks Nicolin