24 Oct
2011
24 Oct
'11
3:09 p.m.
On Mon, Oct 24, 2011 at 11:32:41AM +0800, Axel Lin wrote:
According to the datasheet: The PLL Output clock division ratio is controlled by BIT[5:4] of WM8940_GPIO register(08h). Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.
Applied this and patch 2, thanks.