From: Janusz Krzysztofik jmkrzyszt@gmail.com
Commit ef772f2ee31e ("ARM: OMAP: Fix CONFIG_DEBUG_LL") was supposed to fix low level debugging, most possibly by early enabling UART clocks. The fix actually introduced early reset of most bits of MOD_CONF_CTRL_0 register, with the exception of UART1 and UART2 clock related bits which were set high. However, UART1 clock bit can play different roles on different OMAP1 variants. On OMAP1610 it enables the clock as intended, but on OMAP1510 it switches the clock rate from 12 to 48 MHz. Even worth, for UART2 the bit changes its clock rate also on OMAP1610. As a result, UART rates set by a bootloader can be unintentionally changed early on kernel boot and low level debugging broken, not fixed. Besides, reset of all other bits was not justified.
Don't touch register bits not related to UART clocks. Also, don't touch the bit of UART2 clock. Make sure UART1 and UART3 are enabled early on relevant OMAP1610 machine types while preserving bootloader UART clock rates on others.
Signed-off-by: Janusz Krzysztofik jmkrzyszt@gmail.com Signed-off-by: Arnd Bergmann arnd@arndb.de --- arch/arm/mach-omap1/clock_data.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 36f04da4b939..57d3752babf8 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -766,11 +766,11 @@ int __init omap1_clk_init(void) u32 reg;
#ifdef CONFIG_DEBUG_LL - /* - * Resets some clocks that may be left on from bootloader, - * but leaves serial clocks on. - */ - omap_writel(0x3 << 29, MOD_CONF_CTRL_0); + /* Make sure UART clocks are enabled early */ + if (cpu_is_omap16xx()) + omap_writel(omap_readl(MOD_CONF_CTRL_0) | + CONF_MOD_UART1_CLK_MODE_R | + CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0); #endif
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */