On Fri, Jan 15, 2016 at 10:57 AM, Nicolin Chen nicoleotsuka@gmail.com wrote:
On Fri, Jan 15, 2016 at 10:49:04AM -0800, Caleb Crome wrote:
The watermark is merely a threshold to trigger a DMA request. The only relationship with the burst size is that each burst transfer should not carry more data than the number of empty slots; FIFO under/overflow occurs otherwise. So it's just more efficient and safer to set an identical value to both of them. I don't think it will cause functional problems to set TFWM to 4 and burst size to 1 -- It just lets DMA operate in a single data transfer mode.
If there is no penalty for setting maxburst to 1 (or 2 in the case of dual fifo I think), then should we just set both the watermark and maxburst to 1?
I guess the real difference would be when you're in FIQ mode. In FIQ mode, the penalty of an interrupt per word would be pretty bad, but in DMA mode, if we just set both to 1, we should be fine, right?
There will be much more overhead drawn by frequent DMA transfers. I believe you understand the idea -- less burst size then more DMA request. Each DMA transfer contains a pair of handshaking overhead according to the bus protocol. Apparently the bus will be wasted with lots of handshaking section instead of keep dedicated to data transfer truly. It might work if SSI is the only user of the bus, which we shouldn't assume.
Right, I knew there must be a trade off. So, how about I submit a patch with a fixed value of 4 for whichever platforms you think is correct.
I see the 4 compatibles are: fsl,mpc8610-ssi, fsl,imx51-ssi, fsl,imx35-ssi, and fsl,imx21-ssi.
Shall I submit a patch that sets the value to 4 for for any/all of the above? Should it be different based on whether fiq is enabled. Maybe set it to 4 for whenever DMA is used, and to 13 whenever FIQ is used?
-Caleb