Add the reset controls for all 4 cpu cores.
Signed-off-by: Alex Bee knaerzche@gmail.com --- arch/arm/boot/dts/rockchip/rk312x.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi b/arch/arm/boot/dts/rockchip/rk312x.dtsi index 7aba97b2c990..b195ac525c37 100644 --- a/arch/arm/boot/dts/rockchip/rk312x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk312x.dtsi @@ -34,6 +34,7 @@ cpu0: cpu@f00 { reg = <0xf00>; clock-latency = <40000>; clocks = <&cru ARMCLK>; + resets = <&cru SRST_CORE0>; operating-points = < /* KHz uV */ 816000 1000000 @@ -45,18 +46,21 @@ cpu1: cpu@f01 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf01>; + resets = <&cru SRST_CORE1>; };
cpu2: cpu@f02 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf02>; + resets = <&cru SRST_CORE2>; };
cpu3: cpu@f03 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf03>; + resets = <&cru SRST_CORE3>; }; };