> + if (xcsr & FSL_SAI_CSR_FWF) > + dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); > + > + if (xcsr & FSL_SAI_CSR_FRF) > + dev_dbg(dev, "isr: Transmit FIFO watermark has been
reached\n");
> +
While are these ones really needed to clear manually ?
The reference manual doesn't mention about the requirement. So SAI
should
do
the self-clearance.
Yes, I do think we should let it do the self-clearance, and shouldn't
interfere
of them...
SAI is supposed to ignore the interference, isn't it?
Maybe, but I'm not very sure. And these bits are all writable and readable.
Double-confirmed? Because FWF and FRF should be read-only bits.
So let's just ignore the clearance of these bits in isr().
+++++ SAI Transmit Control Register (I2S1_TCSR) : 32 : R/W : 0000_0000h -----
I have checked in the Vybrid and LS1 SoC datasheets, and they are all the Same as above, and nothing else.
Have I missed ?