Hi Geert
On Tue, Jun 21, 2022 at 09:03:25AM +0200, Geert Uytterhoeven wrote:
Hi Serge,
On Mon, Jun 20, 2022 at 10:56 PM Serge Semin fancer.lancer@gmail.com wrote:
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
[...]
spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1You can just use a more relaxed constraint "enum: [1 2 4 8]" here irrespective from the compatible string. The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. So let's keep the compatible-string-independent "patternProperties" here but just extend the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width" properties values.
Note the DW APB SSI/AHB SSI driver currently doesn't support the enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly activated by means of the corresponding CSR. So most likely the DW AHB SSI controllers need some specific setups too.
That doesn't matter here, as DT describes hardware, not software limitations.
Can't argue with that.) My note regarding the current DW APB SSI driver was mainly addressed for the Canaan K210 users, since should the SoC-based board really have the Quad Tx/Rx SPI bus most likely the interface won't work with the full bandwidth. So it is a good reason to perform the platform research and if possible alter the driver accordingly.
-Sergey
Gr{oetje,eeting}s,
Geert-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds