From: "derek.fang" derek.fang@realtek.com
DAI Wclk of rt5682 only supports 48000Hz output so far, this patch lets it support 44100Hz.
Signed-off-by: derek.fang derek.fang@realtek.com --- sound/soc/codecs/rt5682.c | 49 ++++++++++++++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 18 deletions(-)
diff --git a/sound/soc/codecs/rt5682.c b/sound/soc/codecs/rt5682.c index 5959b6a..f9d8d8c 100644 --- a/sound/soc/codecs/rt5682.c +++ b/sound/soc/codecs/rt5682.c @@ -2461,8 +2461,8 @@ static int rt5682_set_bias_level(struct snd_soc_component *component,
#ifdef CONFIG_COMMON_CLK #define CLK_PLL2_FIN 48000000 -#define CLK_PLL2_FOUT 24576000 #define CLK_48 48000 +#define CLK_44 44100
static bool rt5682_clk_check(struct rt5682_priv *rt5682) { @@ -2544,13 +2544,22 @@ static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, struct rt5682_priv *rt5682 = container_of(hw, struct rt5682_priv, dai_clks_hw[RT5682_DAI_WCLK_IDX]); + struct snd_soc_component *component = rt5682->component; + const char * const clk_name = __clk_get_name(hw->clk);
if (!rt5682_clk_check(rt5682)) return 0; /* - * Only accept to set wclk rate to 48kHz temporarily. + * Only accept to set wclk rate to 44.1k or 48kHz. */ - return CLK_48; + if (rt5682->lrck[RT5682_AIF1] != CLK_48 && + rt5682->lrck[RT5682_AIF1] != CLK_44) { + dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", + __func__, clk_name, CLK_44, CLK_48); + return 0; + } + + return rt5682->lrck[RT5682_AIF1]; }
static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, @@ -2559,13 +2568,22 @@ static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, struct rt5682_priv *rt5682 = container_of(hw, struct rt5682_priv, dai_clks_hw[RT5682_DAI_WCLK_IDX]); + struct snd_soc_component *component = rt5682->component; + const char * const clk_name = __clk_get_name(hw->clk);
if (!rt5682_clk_check(rt5682)) return -EINVAL; /* - * Only accept to set wclk rate to 48kHz temporarily. + * Only accept to set wclk rate to 44.1k or 48kHz. + * It will force to 48kHz if not both. */ - return CLK_48; + if (rate != CLK_48 && rate != CLK_44) { + dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", + __func__, clk_name, CLK_44, CLK_48); + rate = CLK_48; + } + + return rate; }
static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, @@ -2578,6 +2596,7 @@ static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, struct clk *parent_clk; const char * const clk_name = __clk_get_name(hw->clk); int pre_div; + unsigned int clk_pll2_out;
if (!rt5682_clk_check(rt5682)) return -EINVAL; @@ -2600,23 +2619,17 @@ static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, clk_name, CLK_PLL2_FIN);
/* - * It's a temporary limitation. Only accept to set wclk rate to 48kHz. - * It will force wclk to 48kHz even it's not. - */ - if (rate != CLK_48) { - dev_warn(component->dev, "clk %s only support %d Hz output\n", - clk_name, CLK_48); - rate = CLK_48; - } - - /* - * To achieve the rate conversion from 48MHz to 48kHz, PLL2 is needed. + * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, + * PLL2 is needed. */ + clk_pll2_out = rate * 512; rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, - CLK_PLL2_FIN, CLK_PLL2_FOUT); + CLK_PLL2_FIN, clk_pll2_out);
rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, - CLK_PLL2_FOUT, SND_SOC_CLOCK_IN); + clk_pll2_out, SND_SOC_CLOCK_IN); + + rt5682->lrck[RT5682_AIF1] = rate;
pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);