On Wed, Jun 3, 2009 at 9:18 PM, Daniel Mack daniel@caiaq.de wrote:
On Wed, Jun 03, 2009 at 08:33:42PM +0800, Eric Miao wrote:
Make the pxa I2S configuration generic, add support for Left_J, add support for variable frame width like 32fs, 48fs, 64fs and 96fs
Signed-off-by: Paul Shen bshen9@marvell.com Signed-off-by: Eric Miao eric.miao@marvell.com Cc: Daniel Mack daniel@caiaq.de
arch/arm/mach-pxa/include/mach/regs-ssp.h | 14 +++--- sound/soc/pxa/pxa-ssp.c | 62 ++++++++++++++-------------- sound/soc/pxa/pxa-ssp.h | 9 ++++ 3 files changed, 47 insertions(+), 38 deletions(-)
Ok, I tried that code on my board and this is what I had to change there:
The tdm time slot configuration needs to be set again in my board support code just like in your example: snd_soc_set_tdm_slot(cpu_dai, 3, 2).
Mmm.... what would be the preferred way, to let board specific code do this or the I2S configuration code?
And the PXA_SSP_DIV_SCR value needed to be doubled from 4 to 8.
OK, I'll check with SCR, since we used the dithering clock SSACD and SSACDD for the clock.
With that changes, LRCLK is 44100Hz when configured to 44100Hz. But the bitclk is not 64fs anymore but 32fs only (1.41Mhz). Is there any implementation details I miss? What does your codec clock config look like?
Another small thing:
CC sound/soc/pxa/pxa-ssp.o sound/soc/pxa/pxa-ssp.c:186: warning: 'ssp_get_scr' defined but not used
OK, will get rid of that.
Daniel