On Thu, 10 Jan 2019 18:03:24 +0100, Sameer Pujar wrote:
Platforms having multiple hdmi/dp sinks require higher bandwidth to support simultaneous playbacks of higher resolution. If hda controller supports multiple SDO lines, STRIPE can be used to indicate how many of the SDO lines the stream should be striped across.
During stream start stripe control bits are programmed to use given number of sdo lines and the same is cleared during stream stop.
Signed-off-by: Sameer Pujar spujar@nvidia.com Reviewed-by: Mohan Kumar D mkumard@nvidia.com Reviewed-by: Ravindra Lokhande rlokhande@nvidia.com
sound/hda/hdac_stream.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c index b403b05..7dbaecc 100644 --- a/sound/hda/hdac_stream.c +++ b/sound/hda/hdac_stream.c @@ -82,6 +82,7 @@ EXPORT_SYMBOL_GPL(snd_hdac_stream_init); void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start) { struct hdac_bus *bus = azx_dev->bus;
int stripe_ctl;
trace_snd_hdac_stream_start(bus, azx_dev);
@@ -91,6 +92,9 @@ void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
/* enable SIE */ snd_hdac_chip_updatel(bus, INTCTL, 0, 1 << azx_dev->index);
- /* set stripe control */
- stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
- snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, 0, stripe_ctl & 0x3);
Let's use 0x03 as the mask. Also it's safer to clear the mask bits, so something like:
snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, AZX_REG_SD_STRIPE_MASK, stripe_ctl);
/* set DMA start and interrupt mask */ snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_DMA_START | SD_INT_MASK); @@ -107,6 +111,7 @@ void snd_hdac_stream_clear(struct hdac_stream *azx_dev) snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_DMA_START | SD_INT_MASK, 0); snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
- snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, 0x3, 0);
Ditto.
thanks,
Takashi