At Tue, 3 May 2011 14:24:20 +0100, Mark Brown wrote:
On Tue, May 03, 2011 at 03:18:47PM +0200, Takashi Iwai wrote:
Yes, but the core doesn't give how linearly it's stored although its storing order influences on the bulk I/O behavior. In other words, the patches try to put registers partly linearly in magical blocks. But it doesn't guarantee whether the cache block is aligned to what hardware prefers since it's behind the scene.
Eh? I don't follow what you're saying at all, sorry.
The wire formats used by controllers are nailed down by the APIs for the relevant buses and the rest of the register I/O infrastructure. The only extra bit the cache needs to worry about is the set of registers which are present in a given chip and the cache already has information about that (which is what I was telling Dimitris he should use in my direct reply to the patch).
Hrm, then I don't understand why changing the cache management changes the bulk I/O behavior as you described. What's missing there?
Takashi