3 Feb
2012
3 Feb
'12
1:19 p.m.
Hi Mark,
Apologies for missing a few review comments:
snd_soc_write(codec, LM49453_P0_FLL_REF_FREQL_REG, (state->in & 0xff));
snd_soc_write(codec, LM49453_P0_FLL_REF_FREQH_REG,
((state->in >> 8) & 0xff));
snd_soc_write(codec, LM49453_P0_VCO_TARGETLL_REG,
state->out & 0xff);
snd_soc_write(codec, LM49453_P0_VCO_TARGETLH_REG,
(state->out >> 8) & 0xff);
snd_soc_write(codec, LM49453_P0_VCO_TARGETHL_REG,
(state->out >> 16) & 0xff);
snd_soc_write(codec, LM49453_P0_VCO_TARGETHH_REG,
(state->out >> 24) & 0xff);
The above code used to set the reference frequencies for FLL and VCO. Ideally, this code can be removed, because these registers are used for reference only.
switch (lm49453->sysclk) {
case 12288000:
case 26000000:
case 19000000:
/* PLL CLK slection */
pll_clk = ~BIT(4);
break;
case 48000:
case 32576:
/* FLL CLK slection */
pll_clk = BIT(4);
break;
default:
return -EINVAL;
}
The above code used to set for CLOCK type (ie either PLL or FLL). The sysclk is PLL (HIGH FREQ mode) or FLL (LOW FREQ mode). So based on the sysclk, the BIT(4) will be set.
case SND_SOC_BIAS_STANDBY:
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
regcache_sync(lm49453->regmap);
snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
LM49453_PMC_SETUP_CHIP_EN, 0);
break;
case SND_SOC_BIAS_OFF:
snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
LM49453_PMC_SETUP_CHIP_EN, 0);
break;
}
Setting CHIP_EN bit as '0'. In the _STANDBY mode, CHIP_EN bit setting not needed and will remove in the next patch.
Thanks Swami