At Wed, 12 May 2010 09:30:17 +0800, Wu Fengguang wrote:
Currently AZX_MAX_CODECS is defined to 8. Increase it to 10 in order to support the HDMI device indices {3, 7, 8, 9}.
If I understand correctly, the codec slot number is basically independent from the PCM device number assigned. Hence this change shouldn't be necessary unless you really have more than 8 codec chips. Or will be such a high codec address expected soon on new Intel platforms?
The HD audio spec allows up to 14 codecs. So we are still within the hardware capacity.
I thought this was at most 8, so I used the value 0x100 as a special bit flag for probe_mask module option :-< We'd need to change this if we extend the max codecs...
thanks,
Takashi
Signed-off-by: Wu Fengguang fengguang.wu@intel.com
sound/pci/hda/hda_intel.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
--- sound-2.6.orig/sound/pci/hda/hda_intel.c 2010-05-10 09:40:20.000000000 +0800 +++ sound-2.6/sound/pci/hda/hda_intel.c 2010-05-11 13:02:51.000000000 +0800 @@ -267,7 +267,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO #define RIRB_INT_MASK 0x05
/* STATESTS int mask: S3,SD2,SD1,SD0 */ -#define AZX_MAX_CODECS 8 +#define AZX_MAX_CODECS 10 #define AZX_DEFAULT_CODECS 4 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
@@ -866,7 +866,7 @@ static int azx_reset(struct azx *chip, i goto __skip;
/* clear STATESTS */
- azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
azx_writew(chip, STATESTS, STATESTS_INT_MASK);
/* reset controller */ azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
@@ -956,7 +956,7 @@ static void azx_int_clear(struct azx *ch }
/* clear STATESTS */
- azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
azx_writew(chip, STATESTS, STATESTS_INT_MASK);
/* clear rirb status */ azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);