What remains not fully understood for me is the claim that the information already exposed by every driver (in the form of the
minimal
period size) is not useful. I understand that two people are against this idea, so it must be bad. But I must understand why. Is it
because
the minimum period size reported by some drivers (which ones are suspected, if any?) may be a lie?
Does this mean the granularity of most drivers are only one period since most of them cannot reporte the dma position in realtime ?
(e.g. pointer callback of Intel8x0 use a timeout loop to read the last valid index)
The safeguard will be two periods
If some HDA have FIFO size of 192 bytes which is more than the minimum period bytes
Should we limit the start threshold to FIFO threshold or FIFO size ?
Does it need Brust length = 1 for those hda controller to support arbitrary period size ?
Seem only some hda controller can trigger DMA transfer at 1/3 or 2/3 FIFO buffer at different power states and report the dma position in pointer callback
Does snd-oxygen provide this position with granularity which is less than the minimum period size ?