Re: [alsa-devel] [PATCH 6/9] drm: bridge/dw_hdmi: adjust pixel clock values in N calculation

On Fri, Sep 04, 2015 at 07:03:11PM -0700, Doug Anderson wrote:

Then perhaps you shouldn't be using a switch statement. You won't catch all values that are within .05% of (25.2 / 1.001).

No.

The clock rates you get ultimately come from the EDID via either the detailed timing modes or from the CEA mode IDs, which are then looked up in tables in the DRM EDID parsing code.

Either way, you will end up with 25175 and not 25170 or something strange based on what the platform does.