2 Apr
2009
2 Apr
'09
9:39 a.m.
On Wed, Apr 1, 2009 at 3:10 PM, Mark Brown broonie@sirena.org.uk wrote:
switch (cmd) {case SNDRV_PCM_TRIGGER_START:case SNDRV_PCM_TRIGGER_RESUME:case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:aic3x->running[substream->stream] = 1;break;Hrm, does the chip support asymmetric configurations for playback and capture?
My two cents: It supports different sampling rates for ADC and DAC but
I don't believe there is practical use or HW doing this. In this setup there is separate word clock signal on GPIO1 for ADC.
Unfortunately I'm bit off from the actual issue here but I remember some TI codec had requirement to keep DAC/ADC off while changing the configuration...
Jarkko