At Wed, 16 Mar 2011 11:51:00 +0100, David Henningsson wrote:
Here's something I stumbled upon, while debugging something probably unrelated. I don't exactly know the implications of failing multiple stream synchronisation (is that something we commonly use?), or the implications of writing to a register that is "Reserved" in the HDA Spec (can there be crazy vendor magic in there we're unwillingly messing with?).
Perhaps someone else knows more and can tell if this is something that is actually important.
Hrm, it seems that this register was changed at some time. In the old ICH6 datasheet, based on which I wrote the driver, shows SSYNC is 0x34. I checked ICH7 and ICH9, ICH10 datasheet, and all show 0x34, too.
Meanwhile SCH datasheet says it's 0x38, just like HD-audio spec 1.0. So, I'm not sure whether we can change this. We should fix this once when we confirm with a hardware that this is really a bogus value.
thanks,
Takashi
-- David Henningsson, Canonical Ltd. http://launchpad.net/~diwic [2 0001-ALSA-HDA-Correct-address-for-SYNC-register.patch <text/x-patch (7bit)>]
From d7ade361618ee99b89a82b84b035d345ef7a1bd9 Mon Sep 17 00:00:00 2001
From: David Henningsson david.henningsson@canonical.com Date: Wed, 16 Mar 2011 11:35:11 +0100 Subject: [PATCH] ALSA: HDA: Correct address for SYNC register
The SSYNC register is located at address 0x38 according to the HDA specification.
Cc: stable@kernel.org Signed-off-by: David Henningsson david.henningsson@canonical.com
sound/pci/hda/hda_intel.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 70a9d32..ab3f654 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -176,7 +176,7 @@ MODULE_DESCRIPTION("Intel HDA driver"); #define ICH6_REG_INTCTL 0x20 #define ICH6_REG_INTSTS 0x24 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ -#define ICH6_REG_SYNC 0x34 +#define ICH6_REG_SYNC 0x38 #define ICH6_REG_CORBLBASE 0x40 #define ICH6_REG_CORBUBASE 0x44
#define ICH6_REG_CORBWP 0x48
1.7.1