Re: [alsa-devel] Setting some clocks back to DUMMY fixes spdif output on imx6q wandboard rev B1

El Wed, Aug 31, 2016 at 10:11:13AM -0300, Fabio Estevam deia:

2. SPDIF clock rate not accurate. Probably using PLL4 as SPDIF source

would help to get more accurate SPDIF clock rates.

Could you please try the untested change?

--- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -623,7 +623,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) pr_warn("failed to set up CLKO: %d\n", ret);

    /* Audio-related clocks configuration */

•   clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL],
  

clk[IMX6QDL_CLK_PLL3_PFD3_454M]);

•   clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL],
  

clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);

    /* All existing boards with PCIe use LVDS1 */
    if (IS_ENABLED(CONFIG_PCI_IMX6))

I'm going to try. I'll take a while. I'll report the result later.

Thank you very much.