On 4/30/15 9:36 AM, Mark Brown wrote:
On Thu, Apr 30, 2015 at 10:09:41AM +0530, Vinod Koul wrote:
On Wed, Apr 29, 2015 at 06:50:14PM -0500, Pierre-Louis Bossart wrote:
That said I am not sure how this code would work on SKL. Vinod, isn't this for BXT only? how do you get 19.2 on SKL, shouldn't you guys use a 24 MHz root frequency to find the divider?
And regardless you should make sure that the actual blck does not exceed the maximum serial bit-rate supported by the SOC (AC timing).
Yes botha re valid points. But I do rember one of the platforms has 10.2 and another has 25, so we need to be agnostic here and do compare, or use ACPI blobs :)
If this is under the control of the system integrators then I'd suggest you're going to see the configuration being used.
It's an SOC/chipset parameter that can't be changed, not sure why it would come from ACPI - it's really frozen in silicon. The code can remain generic but needs to have an initialization for the root frequency that depends on the SOC/chipset. Rethinking on the bclock check, I withdraw my comment, it's impractical since there can be all sorts of 'optimizations' or limitations that can't be modeled here in this generic code. This check should be done elsewhere with additional platform information.