At Wed, 29 Apr 2015 01:24:25 +0530, Vinod Koul wrote:
From: Jeeja KP jeeja.kp@intel.com
This patch adds new registers as per HD audio Spec like capability registers for processing pipe, software position based FIFO, Multiple Links and Global Time Synchronization.
Signed-off-by: Jeeja KP jeeja.kp@intel.com Signed-off-by: Vinod Koul vinod.koul@intel.com
Should I merge this patch now to topic/hda branch? This looks like the only patch changing the hda core code, the rest are all hda_soc specific.
Or, feel free to take my ack: Acked-by: Takashi Iwai tiwai@suse.de
Takashi
include/sound/hda_register.h | 87 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+)
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index 4f6d3fce6ee6..dced67f5c35f 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -28,6 +28,10 @@ #define AZX_REG_STATESTS 0x0e #define AZX_REG_GSTS 0x10 #define AZX_GSTS_FSTS (1 << 1) /* flush status */ +#define AZX_REG_GCAP2 0x12 +#define AZX_REG_LLCH 0x14 +#define AZX_REG_OUTSTRMPAY 0x18 +#define AZX_REG_INSTRMPAY 0x1A #define AZX_REG_INTCTL 0x20 #define AZX_REG_INTSTS 0x24 #define AZX_REG_WALLCLK 0x30 /* 24Mhz source */ @@ -81,6 +85,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_SD_FIFOW 0x0e #define AZX_REG_SD_FIFOSIZE 0x10 #define AZX_REG_SD_FORMAT 0x12 +#define AZX_REG_SD_FIFOL 0x14 #define AZX_REG_SD_BDLPL 0x18 #define AZX_REG_SD_BDLPU 0x1c
@@ -134,6 +139,88 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_MAX_CORB_ENTRIES 256 #define AZX_MAX_RIRB_ENTRIES 256
+#define AZX_REG_CAP_HDR 0x0 +#define CAP_HDR_VER_OFF 28 +#define CAP_HDR_VER_MASK (0xF << CAP_HDR_VER_OFF) +#define CAP_HDR_ID_OFF 16 +#define CAP_HDR_ID_MASK (0xFFF << CAP_HDR_ID_OFF) +#define CAP_HDR_NXT_PTR_MASK 0xFFFF
+/* registers of Software Position Based FIFO Capability Structure */ +#define SPB_CAP_ID 0x4 +#define AZX_REG_SPB_BASE_ADDR 0x700 +#define AZX_REG_SPB_SPBFCH 0x00 +#define AZX_REG_SPB_SPBFCCTL 0x04 +/* Base used to calculate the iterating register offset */ +#define SPB_BASE 0x08 +/* Interval used to calculate the iterating register offset */ +#define SPB_INTERVAL 0x08
+/* registers of Global Time Synchronization Capability Structure */ +#define GTS_CAP_ID 0x1 +#define AZX_REG_GTS_GTSCH 0x00 +#define AZX_REG_GTS_GTSCD 0x04 +#define AZX_REG_GTS_GTSCTLAC 0x0C +#define GTS_BASE 0x20 +#define GTS_INTERVAL 0x20
+/* registers for Processing Pipe Capability Structure */ +#define PP_CAP_ID 0x3 +#define AZX_REG_PP_PPCH 0x10 +#define AZX_REG_PP_PPCTL 0x04 +#define PPCTL_PIE (1<<31) +#define PPCTL_GPROCEN (1<<30) +/* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */ +#define PPCTL_PROCEN(_X_) (1<<(_X_))
+#define AZX_REG_PP_PPSTS 0x08
+#define PPHC_BASE 0x10 +#define PPHC_INTERVAL 0x10
+#define AZX_REG_PPHCLLPL 0x0 +#define AZX_REG_PPHCLLPU 0x4 +#define AZX_REG_PPHCLDPL 0x8 +#define AZX_REG_PPHCLDPU 0xC
+#define PPLC_BASE 0x10 +#define PPLC_MULTI 0x10 +#define PPLC_INTERVAL 0x10
+#define AZX_REG_PPLCCTL 0x0 +#define PPLCCTL_STRM_BITS 4 +#define PPLCCTL_STRM_SHIFT 20 +#define REG_MASK(bit_num, offset) \
- (((1 << (bit_num)) - 1) << (offset))
+#define PPLCCTL_STRM_MASK \
- REG_MASK(PPLCCTL_STRM_BITS, PPLCCTL_STRM_SHIFT)
+#define PPLCCTL_RUN (1<<1) +#define PPLCCTL_STRST (1<<0)
+#define AZX_REG_PPLCFMT 0x4 +#define AZX_REG_PPLCLLPL 0x8 +#define AZX_REG_PPLCLLPU 0xC
+/* registers for Multiple Links Capability Structure */ +#define ML_CAP_ID 0x2 +#define AZX_REG_ML_MLCH 0x00 +#define AZX_REG_ML_MLCD 0x04 +#define ML_BASE 0x40 +#define ML_INTERVAL 0x40
+#define AZX_REG_ML_LCAP 0x00 +#define AZX_REG_ML_LCTL 0x04 +#define AZX_REG_ML_LOSIDV 0x08 +#define AZX_REG_ML_LSDIID 0x0C +#define AZX_REG_ML_LPSOO 0x10 +#define AZX_REG_ML_LPSIO 0x12 +#define AZX_REG_ML_LWALFC 0x18 +#define AZX_REG_ML_LOUTPAY 0x20 +#define AZX_REG_ML_LINPAY 0x30
+#define MLCTL_SPA (1<<16) +#define MLCTL_CPA 23
/*
- helpers to read the stream position
*/
1.7.9.5