On Mon, Apr 03, 2017 at 04:31:59PM -0700, Caleb Crome wrote:
What's your test case for the alignment?
I'm not sure what you are asking. The test case I'm testing is: connect SSI to AUD4 on wandboard & physically connect TX -> RX. (as per https://github.com/ccrome/linux-caleb-dev/wiki), then use atest to verify bit-perfection of TX->RX transmission.
So your test case involve both TX and RX. That's why this change would impact it. My understanding is: because you can not enable TX and RX in the same time from user space but only through two separate back-to-back system calls. So when the 2nd system call happens (RX for example), the RE bit, supposed to be enabled by this 2nd system call, has already been set by the 1st TX system call -- there's some random data in the RX FIFO already.
regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
regmap_update_bits(regs, CCSR_SSI_SCR,CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);However, this patch seems to merely set the RE bit. It shouldn't affect that test case since the SSIEN bit is still set prior to the TE bit.
Heh, well, this patch causes audio to be utterly broken on multi-channel audio :-/
If possible, could you try to confirm what's the diff between the two SCR values of before-regmap and after-regmap in your case?