Re: [RFC] ASoC: fsl_sai: Do not set MCTL_MCLK_EN based on the number of registers

6 Jul 2023

Hi Shengjiu,
On Thu, Jul 6, 2023 at 10:18 AM Fabio Estevam festevam@gmail.com wrote:
...
From: Fabio Estevam festevam@denx.de
Since commit ff87d619ac18 ("ASoC: fsl_sai: Enable MCTL_MCLK_EN bit for
master mode") Andreas reports that on an i.MX8MP-based system where
MCLK needs to be an input, the MCLK pin is actually an output, despite
not having the 'fsl,sai-mclk-direction-output' property present in the
devicetree.
This commit explains the following:
"On i.MX8MM, the MCTL_MCLK_EN bit it is not only the gate
for MCLK output to PAD, but also the gate bit between
root clock and SAI module, So it is need to be enabled
for master mode, otherwise there is no bclk generated."
As far as I can see, the i.MX8MM Reference Manual only talks about
this bit controlling the MCLK direction.
Is there any documentation that explains this clock gate control functionality?
...
Currently, the decision of using MCTL_MCLK_EN as a clock gate is based
on the number of SAI registers present on a platform.
This is fragile as it causes issues on i.MX8MP, for example.
Fix the problem by introducing a new boolean mclk_en_gates_clock member in
the fsl_sai_soc_data structure that indicates that the MCTL_MCLK_EN bit
also acts as a gate between the root clock and the SAI block.
This allows i.MX8MM to turn on FSL_SAI_MCTL_MCLK_EN as intended and other
SoCs such as i.MX8MP can still use MCLK as input.
Fixes: ff87d619ac18 ("ASoC: fsl_sai: Enable MCTL_MCLK_EN bit for master mode")
Reported-by: Andreas Henriksson andreas@fatal.se
Signed-off-by: Fabio Estevam festevam@denx.de
Signed-off-by: Fabio Estevam festevam@denx.de
Hi Shengjiu,
Is imx8mm the only SoC that needs mclk_en_gates_clock = true?
What about imx8mn and imx93?
sound/soc/fsl/fsl_sai.c | 12 +++++++++++-
 sound/soc/fsl/fsl_sai.h |  1 +
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 5e09f634c61b..e4dc6964f011 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -507,7 +507,7 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
                                   savediv / 2 - 1);
        }

  if (sai->soc_data->max_register >= FSL_SAI_MCTL) {




  if (sai->soc_data->mclk_en_gates_clock) {
          /* SAI is in master mode at this point, so enable MCLK */
          regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
                             FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);



Also, why is FSL_SAI_MCTL_MCLK_EN set in two places (here and inside probe)?

    