Removing these 3 usleep ranges is working now. Although I have a doubt for applying this patch on all chips. There have been a number of boards released after this particular board, but nobody else is facing this problem. Since spec does not specify a max on deasserting RST, some boards might actually take more than 100uS to reset. Will this patch work for those boards?
@@ -1149,7 +1149,7 @@ timeout = jiffies + msecs_to_jiffies(100); while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) && time_before(jiffies, timeout)) - usleep_range(500, 1000); + cpu_relax(); }
/* exit link reset */ @@ -1162,7 +1162,7 @@ timeout = jiffies + msecs_to_jiffies(100); while (!azx_readb(chip, GCTL) && time_before(jiffies, timeout)) - usleep_range(500, 1000); + cpu_relax(); }
/* reset codec link */ @@ -1180,7 +1180,7 @@ /* delay for >= 100us for codec PLL to settle per spec * Rev 0.9 section 5.5.1 */ - usleep_range(500, 1000); + //usleep_range(500, 1000);
/* Bring controller out of reset */ azx_exit_link_reset(chip);