MCLK input is needed when accessing any register after enabling SYSCLK.
This also fixes imbalance of clk_enable / clk_disable when transitioning between ON -> STANDBY -> ON bias levels.
Signed-off-by: Michał Mirosław mirq-linux@rere.qmqm.pl --- sound/soc/codecs/wm8904.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index 2813b7f6a58e..9f0167a39e51 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -1852,9 +1852,6 @@ static int wm8904_set_bias_level(struct snd_soc_component *component,
switch (level) { case SND_SOC_BIAS_ON: - ret = clk_prepare_enable(wm8904->mclk); - if (ret) - return ret; break;
case SND_SOC_BIAS_PREPARE: @@ -1879,6 +1876,15 @@ static int wm8904_set_bias_level(struct snd_soc_component *component, return ret; }
+ ret = clk_prepare_enable(wm8904->mclk); + if (ret) { + dev_err(component->dev, + "Failed to enable MCLK: %d\n", ret); + regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), + wm8904->supplies); + return ret; + } + regcache_cache_only(wm8904->regmap, false); regcache_sync(wm8904->regmap);